How to architect low latency with NVMe at PB scale for AI & ML workloads
Date/Time: Monday, August 19th, 2019 | 09 AM PST
Presenter: Stefaan Vervaet, Solutions Leader, Western Digital
For those looking at implementing Machine learning, Artificial Intelligence or high performance workloads, low latency at scale is crucial to stay competitive. The flash optimized NVMe protocol has been on the market for multiple years now and has been instrumental in delivering the latency and throughput performance required to keep up with these high velocity performance workloads. The key to success, is in how you architect this NVMe enabled storage tier from day one to maintain the benefits it provides, as you scale up your performance and your capacity needs. The majority of scale-out file and block solutions are not designed to take advantage of this new technology at scale. This new solution of Excelero and Western Digital addresses exactly this challenge.
Join experts from Western Digital and Excelero and learn how to:
- Architect a scale-out NVMe architecture
- Deliver microsecond latency at PB scale
- Deliver TB/s in performance to feed the hungry GPUs